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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

Part of the Computer Architecture and Design Methodologies Book Series

DOI: 10.1007/978-981-10-1073-6

ISBN: 978-981-10-1072-9

Publisher: Springer Singapore - Springer Journals

Jun 24, 2017

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Introduction

Wang, Zheng; Chattopadhyay, Anupam

Pages: 1 –4

[The last few decades have witnessed continuous scaling of CMOS technology, guided by Moore’s Law [136] (G.E. Moore, 38(8), 114 ff, 1965. IEEE Solid-State Circuits Newsl., 3(20), 33–35, 2006), to support devices with higher speed, less area, and less power.]
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Background

Wang, Zheng; Chattopadhyay, Anupam

Pages: 5 –10

[In this chapter, fundamental knowledge on reliability are discussed, including reliability definition, fault classification and fault models. In the next soft error and its evaluation metrics are elaborated, which is heavily used in the following chapters.]
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State-of-the-Art

Wang, Zheng; Chattopadhyay, Anupam

Pages: 11 –28

[In this chapter, the related work of this book is elaborated. Initially, fault injection techniques are discussed. Following that, major high-level reliability estimation techniques are briefly illustrated.]
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High-Level Fault Injection and Simulation

Wang, Zheng; Chattopadhyay, Anupam

Pages: 29 –80

[In this chapter, high-level fault injection technique for generic architecture models is presented, which provides an experimental setup for reliability estimation and exploration. First, the architectural fault injector is illustrated in Sect. 4.1. After that, the system-level fault injector is...
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Architectural Reliability Estimation

Wang, Zheng; Chattopadhyay, Anupam

Pages: 81 –117

[In this chapter, three high-level reliability estimation techniques are illustrated which fast characterize the effects of errors on processor architecture.]
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Architectural Reliability Exploration

Wang, Zheng; Chattopadhyay, Anupam

Pages: 119 –153

[In this chapter, three architecture-level fault tolerant techniques are presented. In Sect. 6.1 opportunistic redundancy is proposed to protect the algorithmic units of embedded processor with a low performance penalty. In Sect. 6.2 asymmetric redundancy is proposed to protect the memory...
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System-Level Reliability Exploration

Wang, Zheng; Chattopadhyay, Anupam

Pages: 155 –176

[System-level reliability focuses on the problem of executing specific applications correctly on multi/many core systems. The literature on such issues can be classified in two directions: reliable task mapping and reliable network design. In this chapter two techniques to enhance reliability in...
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Conclusion and Outlook

Wang, Zheng; Chattopadhyay, Anupam

Pages: 177 –179

[Continuous technology scaling in semiconductor industry forces reliability as a serious design concern in the era of nanoscale computing. Traditional low-level reliability estimation and fault tolerant techniques neither address the huge design complexity of modern system-on-chip nor consider...

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