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1990 Workshop on Logic Level Modeling for ASICs final report

1990 Workshop on Logic Level Modeling for ASICs final report The goal for the Logic Level Modeling for ASICs Workshop was to provide an interchange of ideas between people working on ASIC logic level models. Logic Level Models use discrete values at discrete time steps. A simulation or analysis model performs an evaluation based upon values present at ports and upon internal state. Therefore, the workshop discussions centered upon topics related to simulation and analysis based upon discrete logic values and discrete time steps. The workshop goal was achieved by including people from ASIC foundries, CAE companies, and System designers (i.e. ASIC users.) http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM SIGDA Newsletter Association for Computing Machinery

1990 Workshop on Logic Level Modeling for ASICs final report

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Publisher
Association for Computing Machinery
Copyright
Copyright © 1991 by ACM Inc.
ISSN
0163-5743
DOI
10.1145/126990.126992
Publisher site
See Article on Publisher Site

Abstract

The goal for the Logic Level Modeling for ASICs Workshop was to provide an interchange of ideas between people working on ASIC logic level models. Logic Level Models use discrete values at discrete time steps. A simulation or analysis model performs an evaluation based upon values present at ports and upon internal state. Therefore, the workshop discussions centered upon topics related to simulation and analysis based upon discrete logic values and discrete time steps. The workshop goal was achieved by including people from ASIC foundries, CAE companies, and System designers (i.e. ASIC users.)

Journal

ACM SIGDA Newsletter – Association for Computing Machinery

Published: Jun 1, 1991

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