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`Diagonal' layout methodology

`Diagonal' layout methodology In 1988 MCNC International Workshop on Placement and Routing, I am glad to see the workshop includes a section in title "Combined Placement and Global Routing". Although placement and routing are interdependent, due to computational complexity, they have been historically approached separately. From our experience based on the Berkeley Building-Block Layout System (BBL) Che83, even with very sophisticated placement and routing techniques, the system will not guarantee an appropriate layout if the placement and global routing solutions are mismatched Dai87d. In general, without global routing, predicting routability is difficult if not impossible. One alternative is to deliberately overestimate the routing area and try to reclaim the empty space after the routing Ish85. Another alternative is to ignore the violations of design rules during the routing and rely on a sophisticated chip spacer to resolve the design rule violations, at the same time, to minimize the chip area Che88. Not to mention the complexity and inefficiency of the final chip spacing, the errors due to the mismatch between placement and routing propagate channel by channel (if channel routers are used) or net by net (if area routers used). Another approach is to iterate global routing with placement Ada82, but it is hard to converge since a new placement may result in a new global routing, and they may represent a new mismatch. In other systems, the only way to modify the placement during routing is adjusting two blocks relatively when routing the channel in between Lau85 Cai85. This implies that the topology of placement must keep the same with the only exception as shown in Fig. 1. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM SIGDA Newsletter Association for Computing Machinery

`Diagonal' layout methodology

Dai, W.-M.
ACM SIGDA Newsletter , Volume 18 (2) – Jul 1, 1988
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Publisher
Association for Computing Machinery
Copyright
Copyright © 1988 by ACM Inc.
ISSN
0163-5743
DOI
10.1145/49476.49479
Publisher site
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Abstract

In 1988 MCNC International Workshop on Placement and Routing, I am glad to see the workshop includes a section in title "Combined Placement and Global Routing". Although placement and routing are interdependent, due to computational complexity, they have been historically approached separately. From our experience based on the Berkeley Building-Block Layout System (BBL) Che83, even with very sophisticated placement and routing techniques, the system will not guarantee an appropriate layout if the placement and global routing solutions are mismatched Dai87d. In general, without global routing, predicting routability is difficult if not impossible. One alternative is to deliberately overestimate the routing area and try to reclaim the empty space after the routing Ish85. Another alternative is to ignore the violations of design rules during the routing and rely on a sophisticated chip spacer to resolve the design rule violations, at the same time, to minimize the chip area Che88. Not to mention the complexity and inefficiency of the final chip spacing, the errors due to the mismatch between placement and routing propagate channel by channel (if channel routers are used) or net by net (if area routers used). Another approach is to iterate global routing with placement Ada82, but it is hard to converge since a new placement may result in a new global routing, and they may represent a new mismatch. In other systems, the only way to modify the placement during routing is adjusting two blocks relatively when routing the channel in between Lau85 Cai85. This implies that the topology of placement must keep the same with the only exception as shown in Fig. 1.

Journal

ACM SIGDA Newsletter – Association for Computing Machinery

Published: Jul 1, 1988

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