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What is a 3D Network-on-Chip?

What is a 3D Network-on-Chip? While lithographic advances have made it possible to manufacture chips with ever smaller features (Moore's Law), the cost of the required machinery has been steadily increasing, and speculation is that finer geometries will become, if not technically infeasible, impractically expensive. At the same time, the "More than Moore" paradigm 1 has been advocating the creation of chip value through the integration of functionality beyond standard digital CMOS, for example sensing, radiofrequency, optoelectronics. These two trends meet in "3D" chip integration, whereby multiple dies, independently manufactured in possibly very heterogeneous technologies, are stacked together to provide a large amount of functionality in a small package footprint. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM SIGDA Newsletter Association for Computing Machinery

What is a 3D Network-on-Chip?

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Publisher
Association for Computing Machinery
Copyright
The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc.
ISSN
0163-5743
DOI
10.1145/1862903.1862904
Publisher site
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Abstract

While lithographic advances have made it possible to manufacture chips with ever smaller features (Moore's Law), the cost of the required machinery has been steadily increasing, and speculation is that finer geometries will become, if not technically infeasible, impractically expensive. At the same time, the "More than Moore" paradigm 1 has been advocating the creation of chip value through the integration of functionality beyond standard digital CMOS, for example sensing, radiofrequency, optoelectronics. These two trends meet in "3D" chip integration, whereby multiple dies, independently manufactured in possibly very heterogeneous technologies, are stacked together to provide a large amount of functionality in a small package footprint.

Journal

ACM SIGDA Newsletter – Association for Computing Machinery

Published: Jul 1, 2009

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