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Fast Response, Medium Resolution Digital Event Timer and Range Gate Generator for Satellite Laser Ranging

Fast Response, Medium Resolution Digital Event Timer and Range Gate Generator for Satellite Laser... For our kHz Satellite Laser Ranging (SLR) system in Graz, we developed a fast response, medium resolution Evt Timer to determine laser firing times; and a digital Range Gate Gerator to activate the Single Photon Avalanche Detector (C-SPAD). The Evt Timer has a resolution of about 500 ps, and determines the Evt Times within 20 ns; the Range Gate Gerator produces a range gate pulse with about 500 ps resolution, and with an accuracy of better than 1 ns. Both devices are fully digital, and are implemted within an FPGA circuit. These devices can be used in the prest 2 kHz SLR system, as well as in future higher repetition rate SLR systems. Keywords: Evt Timer, FPGA, SLR, Range Gate Gerator INTRODUCTION SLR systems use short laser pulses to measure distances betwe ground stations and retroreflector equipped satellites to the millimeter level. These activities are coordinated within the International Laser Ranging Service (ILRS), supporting geodetic and geophysical research (Pearlman et al, 2002). An SLR system consists of a laser, a telescope, a ­ single or multiple - photon detector (in Graz: C-SPAD) and a time of flight (TOF) measuremt device. The TOF can be measured with 2 differt methods: With a simple time interval counter, or with evt timers. Time interval counters are not applicable for kHz SLR, because due to the high repetition rate (some kHz) there are always more than 1 pulse ­ up to 300 pulses for high orbit satellites for a 2 kHz SLR system ­ simultaneously traveling betwe SLR station and satellite. The high precision evt timers determine laser firing epochs, and epochs of the returns indepdtly; these epochs are th used to calculate the TOF. Because the ultra high precision Graz E.T. (< 2.5 ps) needs about 400 s to fix the evt time (Kirchner et al, 2000), we developed a much faster (20 ns response time: The completed evt time measuremt is available within 20 ns after the evt), but medium resolution (500 ps) evt timer within the FPGA (Iqbal, 2008), dedicated ­ and accurate ough - for range gating purposes. 144 After detecting a laser start pulse evt time, the expected return evt time is calculated, and loaded into the Range Gate Gerator; which th activates the detector short before arrival of the return photon(s). While this is done at prest with a combination of a digital 100-ns-resolution FPGA counter PLUS a programmable analog delay chip, we implemted now a fully digital Range Gate Gerator into the FPGA - using a 5-ns course counter, and a 500 ps vernier ­ to improve linearity and stability. Both devices were implemted within the Altera FPGA Apex 20K chip on the Graz FPGA card. 2. EVT TIMER IMPLEMTATION The fast response digital evt timer is implemted using a well known vernier method. This method uses a 200 MHz counter and a vernier for the 5 ns intervals. The vernier uses standard s with 500 ps transit time per gate (fig. 2). To implemt a series of idtical, cascaded delay gates we had to disable the automatic optimization of the Quartus Compiler for the Altera FPGA device. The evt pulse (e.g. Laser Start Pulse) starts traveling through several parallel chains of s; each chain consists of an increasing number of s; the next following 5 ns clock pulse is used as a STOP pulse for this simple vernier (fig. 1). Evt Start Clock Stop Measured by vernier Fig. 1. A digital vernier interpolates betwe 5 ns clock pulses. Output Register 1 Stop Gate 1 1 1 1 Stop Gate 0 0 0 0 Stop Gate 0 Evt Stop 1- Delay 2- N- Delay Fig. 2. Evt timer unit, using chains of AND delay gates of increasing lgth. 145 If the start pulse reaches the d of a chain BEFORE the STOP pulse, a "1" is latched into an output register; if not: a "0"... (Fig. 2). The bits in this output register represt a measure for the 0-5 ns interpolation; together with the latched actual reading of the 200 MHz coarse clock this forms a 500 ps resolution evt time. Simulation of such a circuitry gave promising results for the required speed and resolution of this Evt Timer (fig. 3); therefore we implemted this evt timer into the Graz ISA card FPGA; optimizing its floor plan layout to achieve optimal linearity and uniform resolution.. Clock 200 MHz Evt Stop Bit1 Bit2 Bit3 Vernier Time 500 ps Intervals Fig. 3. (A) Vernier measuremt, interpolating 5 ns intervals. 3. EVT TIMER TEST RESULTS We tested the temperature drift of a 100-AND-gate delay chain; it drifted with about 10 ps/C° (Fig. 5), which is quite acceptable considering the required resolution, and the location of the PC / ISA Card / FPGA in the air conditioned laser room. Delay of a 100-AND-Gates Delay Chain vs. Temperature 53760 53730 Distribution of Points Linear (10 ps/C°) 53700 53670 53640 53610 53580 53550 20 25 30 35 Temperature [C°] Fig. 5. Delay of a 100-AND-Gates Delay Chain vs. Temperature. Delay [ps] 146 To evaluate the FPGA evt timer linearity, (fig 6: Test setup) we compared its results with those of our ultra high precision (1.2 ps resolution, < 2.5 ps non-linearity) Graz E.T. (Kirchner et al, 2004). The differces betwe both showed an RMS of 260 - 290 ps. PC Diff GPS 1PPs 10MHz 1PPS 10MHz FPGA Board S/W Fortran MS-DOS DG-535 Pulse Gerator Pulse In Evt Timer 1.2 ps Resolution < 2.5 ps RMS Fig. 6. Test setup to compare Graz E.T. and FPGA ET. Although an evt timing accuracy of < 300 ps is fully sufficit for the purpose of Range Gate Epoch determination, we tested possible improvemts by implemting 4 such Evt Timer Units in parallel (fig. 7) into the FPGA. All 4 evt times are read by PC and averaged there; this average reduces the FPGA evt timer jitter only to 217 ps RMS (instead of the theoretically expected values of about 140 ps), mainly due to the remaining non-linearities within the 5 ns interpolation interval. FPGA FPGA Evt Timer Unit 1 FPGA Evt Timer Unit 2 Averaging in PC Evt FPGA Evt Timer Unit 3 FPGA Evt Timer Unit 4 Fig. 7. 4 Parallel Evt Timers. 4. RANGE GATE GERATOR We used a 200MHz clock and a chain of s to implemt a Range Gate Gerator (programmed via PC) - which gerates a range gate pulse short before the actual return of the laser photons - with a resolution of about 500 ps and an accuracy of < 1ns. 147 The start pulse (fig.8) travels through the chain of s. The output of each gate switches its associated D-Flip-Flop as soon as the start pulse has passed; only ONE out of these D-Flip-Flops is activated by the pre-programmable selection logic, and gerates the Range Gate pulse (fig. 8). Delay 1 Delay 2 D-FF Start pulse Delay 3 D-FF D-FF Delay N Pre-programmed Selection Logic 0 0 1 0 0 0 Range Gate Selection Logic Fig. 8. Block Diagram of Digital Range Gate Gerator. 5. RANGE GATE GERATOR TEST RESULTS Our test setup (fig.9) used a DG535 Pulse Gerator, a Stanford SR620 Time Interval Counter, and a GPS system (1 pps, 10 MHz) to test the linearity of the Range Gate Gerator. PC FPGA Board Pulse In RG-Out GPS 1 PPs 10 MHz 1PPS 10MHz S/W Fortran MS-DOS DG535 Pulse Gerator Pulse In Start Stop SR620 Time Interval Counter Fig. 9. Experimtal set up for Range Gate Gerator Evaluation. We tried 3 differt placemts (floor plan layouts; both manual placemts and/or automatical placemts (Altera), of the s and D-Flip-Flops within the logical cells) of the Range Gate circuitry inside the FPGA to find the optimum linearity (Fig.10); the selected final placemt has the best R-squared value ("R2" in fig. 10) and linearity. RG_ps-Resolution 10000 Delay [ps] (Placemt 1) Delay [ps] (Placemt 2) Delay [ps] (Placemt 3) 7500 R2 = 0,9960 R2 = 0,9945 Delay [ps] R2 = 0,9963 0 0 5 No.of gates in chain 10 15 Fig. 10. Delay Time (ps) vs. Delay Chain Lgth ­ differt placemts of s and DFlip-Flops to optimize linearity. CONCLUSIONS The resolution and non-linearity of this FPGA Evt Timer unit is more than adequate for our purpose of fast Range Gate setting; if higher resolution is required, a multi-channel Evt Timer can be implemted. Due to its high speed ­ the result is available within 20 ns - , it is well suited for the existing 2 kHz SLR system, and also for systems with significantly higher repetition rates, (Sadovnikov, 2000). This Digital Range Gate Gerator is fully adequate for the prest Graz 2 kHz SLR system, and we visage it's use also for higher repetition rate SLR systems. kHz SLR has gained vital interest within the SLR community, and these newly designed devices - FPGA evt timer and range gate gerator - can help to reduce implemtation problems of of prest and future high repetition rate SLR systems. Acknowledgmt Special thanks to Higher Education Commission of Pakistan (HEC) for providing a PHD fellowship for Farhat Iqbal at SLR Graz for this study and research. 149 REFERCES Altera FPGA: several application notes available at Altera website: www.altera.com e.g. (1) analyzing and optimizing the Design Floor plan. (2) Best Practices for Incremtal Compilation Partitions and Floor plan Assignmts. Etc. Iqbal F. (2008): Medium Resolution Evt Timer and Range Gate Gerator in Graz FPGA Card, 16th international Laser Ranging Conferce; Poznan, Poland, Oct. 2008. Kirchner G., Koidl F. (2000): Graz Evt Timing System; Proceedings of 14th Int. Workshop on Laser Ranging, Matera, Italy. Kirchner G., Koidl F. (2004): Graz kHz SLR system: Design, Experices and Results Proceedings of 14th Int. Workshop on Laser Ranging, San Fernando / Spain. Pearlman, M.R., Degnan, J.J., and Bosworth, J.M.(2002):The International Laser Ranging Service; Advances in Space Research, Vol. 30, No. 2, pp. 135-143,DOI:10.1016/S02731177(02)00277-6. Sadovnikov M.A. (2008): Pulse Repetition rate optimization in SLR stations to provide minimum systematic error of reading, 16th international Laser Ranging Conferce Poznan, Poland. Received: 2009-02-27, Reviewed: 2009-07-22, by I. Procházka, Accepted: 2009-08-03. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Artificial Satellites de Gruyter

Fast Response, Medium Resolution Digital Event Timer and Range Gate Generator for Satellite Laser Ranging

Iqbal, F.; Kirchner, G.; Koidl, F.
Artificial Satellites , Volume 43 (4) – Jan 1, 2008
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Abstract

For our kHz Satellite Laser Ranging (SLR) system in Graz, we developed a fast response, medium resolution Evt Timer to determine laser firing times; and a digital Range Gate Gerator to activate the Single Photon Avalanche Detector (C-SPAD). The Evt Timer has a resolution of about 500 ps, and determines the Evt Times within 20 ns; the Range Gate Gerator produces a range gate pulse with about 500 ps resolution, and with an accuracy of better than 1 ns. Both devices are fully digital, and are implemted within an FPGA circuit. These devices can be used in the prest 2 kHz SLR system, as well as in future higher repetition rate SLR systems. Keywords: Evt Timer, FPGA, SLR, Range Gate Gerator INTRODUCTION SLR systems use short laser pulses to measure distances betwe ground stations and retroreflector equipped satellites to the millimeter level. These activities are coordinated within the International Laser Ranging Service (ILRS), supporting geodetic and geophysical research (Pearlman et al, 2002). An SLR system consists of a laser, a telescope, a ­ single or multiple - photon detector (in Graz: C-SPAD) and a time of flight (TOF) measuremt device. The TOF can be measured with 2 differt methods: With a simple time interval counter, or with evt timers. Time interval counters are not applicable for kHz SLR, because due to the high repetition rate (some kHz) there are always more than 1 pulse ­ up to 300 pulses for high orbit satellites for a 2 kHz SLR system ­ simultaneously traveling betwe SLR station and satellite. The high precision evt timers determine laser firing epochs, and epochs of the returns indepdtly; these epochs are th used to calculate the TOF. Because the ultra high precision Graz E.T. (< 2.5 ps) needs about 400 s to fix the evt time (Kirchner et al, 2000), we developed a much faster (20 ns response time: The completed evt time measuremt is available within 20 ns after the evt), but medium resolution (500 ps) evt timer within the FPGA (Iqbal, 2008), dedicated ­ and accurate ough - for range gating purposes. 144 After detecting a laser start pulse evt time, the expected return evt time is calculated, and loaded into the Range Gate Gerator; which th activates the detector short before arrival of the return photon(s). While this is done at prest with a combination of a digital 100-ns-resolution FPGA counter PLUS a programmable analog delay chip, we implemted now a fully digital Range Gate Gerator into the FPGA - using a 5-ns course counter, and a 500 ps vernier ­ to improve linearity and stability. Both devices were implemted within the Altera FPGA Apex 20K chip on the Graz FPGA card. 2. EVT TIMER IMPLEMTATION The fast response digital evt timer is implemted using a well known vernier method. This method uses a 200 MHz counter and a vernier for the 5 ns intervals. The vernier uses standard s with 500 ps transit time per gate (fig. 2). To implemt a series of idtical, cascaded delay gates we had to disable the automatic optimization of the Quartus Compiler for the Altera FPGA device. The evt pulse (e.g. Laser Start Pulse) starts traveling through several parallel chains of s; each chain consists of an increasing number of s; the next following 5 ns clock pulse is used as a STOP pulse for this simple vernier (fig. 1). Evt Start Clock Stop Measured by vernier Fig. 1. A digital vernier interpolates betwe 5 ns clock pulses. Output Register 1 Stop Gate 1 1 1 1 Stop Gate 0 0 0 0 Stop Gate 0 Evt Stop 1- Delay 2- N- Delay Fig. 2. Evt timer unit, using chains of AND delay gates of increasing lgth. 145 If the start pulse reaches the d of a chain BEFORE the STOP pulse, a "1" is latched into an output register; if not: a "0"... (Fig. 2). The bits in this output register represt a measure for the 0-5 ns interpolation; together with the latched actual reading of the 200 MHz coarse clock this forms a 500 ps resolution evt time. Simulation of such a circuitry gave promising results for the required speed and resolution of this Evt Timer (fig. 3); therefore we implemted this evt timer into the Graz ISA card FPGA; optimizing its floor plan layout to achieve optimal linearity and uniform resolution.. Clock 200 MHz Evt Stop Bit1 Bit2 Bit3 Vernier Time 500 ps Intervals Fig. 3. (A) Vernier measuremt, interpolating 5 ns intervals. 3. EVT TIMER TEST RESULTS We tested the temperature drift of a 100-AND-gate delay chain; it drifted with about 10 ps/C° (Fig. 5), which is quite acceptable considering the required resolution, and the location of the PC / ISA Card / FPGA in the air conditioned laser room. Delay of a 100-AND-Gates Delay Chain vs. Temperature 53760 53730 Distribution of Points Linear (10 ps/C°) 53700 53670 53640 53610 53580 53550 20 25 30 35 Temperature [C°] Fig. 5. Delay of a 100-AND-Gates Delay Chain vs. Temperature. Delay [ps] 146 To evaluate the FPGA evt timer linearity, (fig 6: Test setup) we compared its results with those of our ultra high precision (1.2 ps resolution, < 2.5 ps non-linearity) Graz E.T. (Kirchner et al, 2004). The differces betwe both showed an RMS of 260 - 290 ps. PC Diff GPS 1PPs 10MHz 1PPS 10MHz FPGA Board S/W Fortran MS-DOS DG-535 Pulse Gerator Pulse In Evt Timer 1.2 ps Resolution < 2.5 ps RMS Fig. 6. Test setup to compare Graz E.T. and FPGA ET. Although an evt timing accuracy of < 300 ps is fully sufficit for the purpose of Range Gate Epoch determination, we tested possible improvemts by implemting 4 such Evt Timer Units in parallel (fig. 7) into the FPGA. All 4 evt times are read by PC and averaged there; this average reduces the FPGA evt timer jitter only to 217 ps RMS (instead of the theoretically expected values of about 140 ps), mainly due to the remaining non-linearities within the 5 ns interpolation interval. FPGA FPGA Evt Timer Unit 1 FPGA Evt Timer Unit 2 Averaging in PC Evt FPGA Evt Timer Unit 3 FPGA Evt Timer Unit 4 Fig. 7. 4 Parallel Evt Timers. 4. RANGE GATE GERATOR We used a 200MHz clock and a chain of s to implemt a Range Gate Gerator (programmed via PC) - which gerates a range gate pulse short before the actual return of the laser photons - with a resolution of about 500 ps and an accuracy of < 1ns. 147 The start pulse (fig.8) travels through the chain of s. The output of each gate switches its associated D-Flip-Flop as soon as the start pulse has passed; only ONE out of these D-Flip-Flops is activated by the pre-programmable selection logic, and gerates the Range Gate pulse (fig. 8). Delay 1 Delay 2 D-FF Start pulse Delay 3 D-FF D-FF Delay N Pre-programmed Selection Logic 0 0 1 0 0 0 Range Gate Selection Logic Fig. 8. Block Diagram of Digital Range Gate Gerator. 5. RANGE GATE GERATOR TEST RESULTS Our test setup (fig.9) used a DG535 Pulse Gerator, a Stanford SR620 Time Interval Counter, and a GPS system (1 pps, 10 MHz) to test the linearity of the Range Gate Gerator. PC FPGA Board Pulse In RG-Out GPS 1 PPs 10 MHz 1PPS 10MHz S/W Fortran MS-DOS DG535 Pulse Gerator Pulse In Start Stop SR620 Time Interval Counter Fig. 9. Experimtal set up for Range Gate Gerator Evaluation. We tried 3 differt placemts (floor plan layouts; both manual placemts and/or automatical placemts (Altera), of the s and D-Flip-Flops within the logical cells) of the Range Gate circuitry inside the FPGA to find the optimum linearity (Fig.10); the selected final placemt has the best R-squared value ("R2" in fig. 10) and linearity. RG_ps-Resolution 10000 Delay [ps] (Placemt 1) Delay [ps] (Placemt 2) Delay [ps] (Placemt 3) 7500 R2 = 0,9960 R2 = 0,9945 Delay [ps] R2 = 0,9963 0 0 5 No.of gates in chain 10 15 Fig. 10. Delay Time (ps) vs. Delay Chain Lgth ­ differt placemts of s and DFlip-Flops to optimize linearity. CONCLUSIONS The resolution and non-linearity of this FPGA Evt Timer unit is more than adequate for our purpose of fast Range Gate setting; if higher resolution is required, a multi-channel Evt Timer can be implemted. Due to its high speed ­ the result is available within 20 ns - , it is well suited for the existing 2 kHz SLR system, and also for systems with significantly higher repetition rates, (Sadovnikov, 2000). This Digital Range Gate Gerator is fully adequate for the prest Graz 2 kHz SLR system, and we visage it's use also for higher repetition rate SLR systems. kHz SLR has gained vital interest within the SLR community, and these newly designed devices - FPGA evt timer and range gate gerator - can help to reduce implemtation problems of of prest and future high repetition rate SLR systems. Acknowledgmt Special thanks to Higher Education Commission of Pakistan (HEC) for providing a PHD fellowship for Farhat Iqbal at SLR Graz for this study and research. 149 REFERCES Altera FPGA: several application notes available at Altera website: www.altera.com e.g. (1) analyzing and optimizing the Design Floor plan. (2) Best Practices for Incremtal Compilation Partitions and Floor plan Assignmts. Etc. Iqbal F. (2008): Medium Resolution Evt Timer and Range Gate Gerator in Graz FPGA Card, 16th international Laser Ranging Conferce; Poznan, Poland, Oct. 2008. Kirchner G., Koidl F. (2000): Graz Evt Timing System; Proceedings of 14th Int. Workshop on Laser Ranging, Matera, Italy. Kirchner G., Koidl F. (2004): Graz kHz SLR system: Design, Experices and Results Proceedings of 14th Int. Workshop on Laser Ranging, San Fernando / Spain. Pearlman, M.R., Degnan, J.J., and Bosworth, J.M.(2002):The International Laser Ranging Service; Advances in Space Research, Vol. 30, No. 2, pp. 135-143,DOI:10.1016/S02731177(02)00277-6. Sadovnikov M.A. (2008): Pulse Repetition rate optimization in SLR stations to provide minimum systematic error of reading, 16th international Laser Ranging Conferce Poznan, Poland. Received: 2009-02-27, Reviewed: 2009-07-22, by I. Procházka, Accepted: 2009-08-03.

Journal

Artificial Satellites – de Gruyter

Published: Jan 1, 2008

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