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Area, delay and power comparison of fault-tolerant systems with TMR using different voter circuits

Area, delay and power comparison of fault-tolerant systems with TMR using different voter circuits In a current very large-scale integration (VLSI) technology evolution, the reliability issues are the major concern for the improvement of the system. The most fundamental method used for the fault-tolerant system is triple modular redundancy (TMR) in which the majority voter circuit is used to obtain the fault-free response. In this study, the different voter circuits are implemented to analyse the least layout area and lower power dissipation with an applicationspecific integrated circuits (ASIC) approach using the Microwind layout editor tool. This work is carried out with the eight voting circuits including two proposed methods. The application examples such as a 32-bit adder, an unsigned 8x8 array multiplier, bitwise XOR operation and a 3 x 3 high-pass filter are demonstrated to compare the performance of different voters. The simulation results (power, area, delay) for all the four application examples are obtained and compared. Keywords: adders; bitwise XOR; FPGA; high-pass filter; reliability; TMR; voters. Reference to this paper should be made as follows: Elamaran, V. and Upadhyay, H.N. (2017) `Area, delay and power comparison of fault-tolerant systems with TMR using different voter circuits', Int. J. Signal and Imaging Systems Engineering, Vol. 10, Nos. 1/2, pp.63­71. Biographical notes: V. Elamaran http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png International Journal of Signal and Imaging Systems Engineering Inderscience Publishers

Area, delay and power comparison of fault-tolerant systems with TMR using different voter circuits

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Publisher
Inderscience Publishers
Copyright
Copyright © 2017 Inderscience Enterprises Ltd.
ISSN
1748-0698
eISSN
1748-0701
DOI
10.1504/IJSISE.2017.084572
Publisher site
See Article on Publisher Site

Abstract

In a current very large-scale integration (VLSI) technology evolution, the reliability issues are the major concern for the improvement of the system. The most fundamental method used for the fault-tolerant system is triple modular redundancy (TMR) in which the majority voter circuit is used to obtain the fault-free response. In this study, the different voter circuits are implemented to analyse the least layout area and lower power dissipation with an applicationspecific integrated circuits (ASIC) approach using the Microwind layout editor tool. This work is carried out with the eight voting circuits including two proposed methods. The application examples such as a 32-bit adder, an unsigned 8x8 array multiplier, bitwise XOR operation and a 3 x 3 high-pass filter are demonstrated to compare the performance of different voters. The simulation results (power, area, delay) for all the four application examples are obtained and compared. Keywords: adders; bitwise XOR; FPGA; high-pass filter; reliability; TMR; voters. Reference to this paper should be made as follows: Elamaran, V. and Upadhyay, H.N. (2017) `Area, delay and power comparison of fault-tolerant systems with TMR using different voter circuits', Int. J. Signal and Imaging Systems Engineering, Vol. 10, Nos. 1/2, pp.63­71. Biographical notes: V. Elamaran

Journal

International Journal of Signal and Imaging Systems Engineering – Inderscience Publishers

Published: Jan 1, 2017

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