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A Practical Approach to VLSI System on Chip (SoC) DesignSoC Design for Testability (DFT)

A Practical Approach to VLSI System on Chip (SoC) Design: SoC Design for Testability (DFT) [This chapter describes the need for design testability and design for testability (DFT) of SOC. It explains the methodology widely followed for SOC DFT and the automatic test pattern generation (ATPG) techniques. It covers the major challenges faced during SOC DFT. Advanced DFT techniques such as test compression and at-speed tests are covered here.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Practical Approach to VLSI System on Chip (SoC) DesignSoC Design for Testability (DFT)

Chakravarthi, Veena S.
Springer Journals — Dec 14, 2022
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20 pages

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Publisher
Springer International Publishing
Copyright
© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2022
ISBN
978-3-031-18362-1
Pages
113 –133
DOI
10.1007/978-3-031-18363-8_6
Publisher site
See Chapter on Publisher Site

Abstract

[This chapter describes the need for design testability and design for testability (DFT) of SOC. It explains the methodology widely followed for SOC DFT and the automatic test pattern generation (ATPG) techniques. It covers the major challenges faced during SOC DFT. Advanced DFT techniques such as test compression and at-speed tests are covered here.]

Published: Dec 14, 2022

Keywords: DFT MODE; LBIST; PMBIST; Boundary scan; JTAG; IEEE 1149.1/6; ATPG; MISR; PRPG; Scan compression

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