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A Practical Introduction to PSLClocks

A Practical Introduction to PSL: Clocks [Up until now, we have examined cycle-based traces — we have not explicitly mentioned the clock. The clock operator allows you to describe traces that are based on “ticks” of one or more clock signals. For example, consider the requirement “two consecutive requests (assertions of signal req) are not allowed” in a design clocked on the rising edge of signal clk that behaves as shown in Trace 6.1(i). There are three “ticks” of the clock signal clk in Trace 6.1(i), each of them three cycles wide.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Practical Introduction to PSLClocks

Part of the Series on Integrated Circuits and Systems Book Series
Springer Journals — Jan 1, 2006
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17 pages

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Publisher
Springer US
Copyright
© Springer Science+Business Media, LLC 2006
ISBN
978-0-387-35313-5
Pages
65 –82
DOI
10.1007/978-0-387-36123-9_6
Publisher site
See Chapter on Publisher Site

Abstract

[Up until now, we have examined cycle-based traces — we have not explicitly mentioned the clock. The clock operator allows you to describe traces that are based on “ticks” of one or more clock signals. For example, consider the requirement “two consecutive requests (assertions of signal req) are not allowed” in a design clocked on the rising edge of signal clk that behaves as shown in Trace 6.1(i). There are three “ticks” of the clock signal clk in Trace 6.1(i), each of them three cycles wide.]

Published: Jan 1, 2006

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