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A Roadmap for Formal Property VerificationLanguages for Temporal Properties

A Roadmap for Formal Property Verification: Languages for Temporal Properties [Formal verification makes sense only when we have a formal specification that acts as the reference for verifying the correctness of a given design implementation. The notion of formal speci.cations is not new. Fundamentally we are aware that the functionality of all digital circuits may be formally expressed in terms of Boolean functions. For example, a half adder which receives two 1-bit inputs, a and b and produces two 1-bit outputs, namely the sum, s, and the carry c may be specified completely by the Boolean functions:] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

A Roadmap for Formal Property VerificationLanguages for Temporal Properties

DasGupta, Pallab
Springer Journals — Jan 1, 2006
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39 pages

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Publisher
Springer Netherlands
Copyright
© Springer 2006
ISBN
978-1-4020-4757-2
Pages
19 –58
DOI
10.1007/978-1-4020-4758-9_2
Publisher site
See Chapter on Publisher Site

Abstract

[Formal verification makes sense only when we have a formal specification that acts as the reference for verifying the correctness of a given design implementation. The notion of formal speci.cations is not new. Fundamentally we are aware that the functionality of all digital circuits may be formally expressed in terms of Boolean functions. For example, a half adder which receives two 1-bit inputs, a and b and produces two 1-bit outputs, namely the sum, s, and the carry c may be specified completely by the Boolean functions:]

Published: Jan 1, 2006

Keywords: State Machine; Boolean Function; Linear Temporal Logic; Sequence Expression; Computation Tree Logic

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