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Designing TSVs for 3D Integrated CircuitsAnalysis and Mitigation of TSV-Induced Substrate Noise

Designing TSVs for 3D Integrated Circuits: Analysis and Mitigation of TSV-Induced Substrate Noise [TSVs are a major source of substrate noise that threatens the performance of neighboring devices. In addition, TSV noise increases leakage current, which increases static power consumption and can erroneously switch transistors off or on [91]. A “keep out” zone, specified through layout rules, is thus required to shield devices from neighboring TSVs.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

Designing TSVs for 3D Integrated CircuitsAnalysis and Mitigation of TSV-Induced Substrate Noise

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Publisher
Springer New York
Copyright
© The Authors 2013
ISBN
978-1-4614-5507-3
Pages
15 –26
DOI
10.1007/978-1-4614-5508-0_3
Publisher site
See Chapter on Publisher Site

Abstract

[TSVs are a major source of substrate noise that threatens the performance of neighboring devices. In addition, TSV noise increases leakage current, which increases static power consumption and can erroneously switch transistors off or on [91]. A “keep out” zone, specified through layout rules, is thus required to shield devices from neighboring TSVs.]

Published: Aug 27, 2012

Keywords: Liner Thickness; Small Aspect Ratio; Substrate Noise; Static Power Consumption; Dielectric Liner

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