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Designing TSVs for 3D Integrated CircuitsIntroduction

Designing TSVs for 3D Integrated Circuits: Introduction [Moore’s law has inspired the growth of integrated circuit (IC) technology since its inception in 1965 [75]. Each new technology node produces smaller and faster devices keeping pace with Moore’s prediction of 2 ×scaling every 18 months. The exponential decrease in feature size, from 10 μm [87] to 22 nm [20] over the past four decades, has resulted in an astronomical performance increase. For this trend to continue, significant challenges need to be overcome in several key areas [74]. IC technology has evolved from a device-centric technology to one where interconnect also plays a critical role. The latency of interconnect dominates that of transistors [70]. Oxide thickness of a metal oxide semiconductor field effect transistor (MOSFET) determines the size and the leakage current of a transistor. Oxide thickness approaching atomic levels imposes a practical bound on the leakage current and hence limits transistor sizes [93, 105]. Exponential increase in capital cost, to set up a foundry, poses a threat to the viability of future technology scaling [26].] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

Designing TSVs for 3D Integrated CircuitsIntroduction

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Publisher
Springer New York
Copyright
© The Authors 2013
ISBN
978-1-4614-5507-3
Pages
1 –5
DOI
10.1007/978-1-4614-5508-0_1
Publisher site
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Abstract

[Moore’s law has inspired the growth of integrated circuit (IC) technology since its inception in 1965 [75]. Each new technology node produces smaller and faster devices keeping pace with Moore’s prediction of 2 ×scaling every 18 months. The exponential decrease in feature size, from 10 μm [87] to 22 nm [20] over the past four decades, has resulted in an astronomical performance increase. For this trend to continue, significant challenges need to be overcome in several key areas [74]. IC technology has evolved from a device-centric technology to one where interconnect also plays a critical role. The latency of interconnect dominates that of transistors [70]. Oxide thickness of a metal oxide semiconductor field effect transistor (MOSFET) determines the size and the leakage current of a transistor. Oxide thickness approaching atomic levels imposes a practical bound on the leakage current and hence limits transistor sizes [93, 105]. Exponential increase in capital cost, to set up a foundry, poses a threat to the viability of future technology scaling [26].]

Published: Aug 27, 2012

Keywords: Integrate Circuit; Oxide Thickness; Power Delivery; Technology Node; SRAM Cell

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