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Fault Tolerant Computer ArchitectureIntroduction

Fault Tolerant Computer Architecture: Introduction [For many years, most computer architects have pursued one primary goal: performance. Architects have translated the ever-increasing abundance of ever-faster transistors provided by Moore’s law into remarkable increases in performance. Recently, however, the bounty provided by Moore’s law has been accompanied by several challenges that have arisen as devices have become smaller, including a decrease in dependability due to physical faults. In this book, we focus on the dependability challenge and the fault tolerance solutions that architects are developing to overcome it.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

Fault Tolerant Computer ArchitectureIntroduction

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Publisher
Springer International Publishing
Copyright
© Springer Nature Switzerland AG 2009
ISBN
978-3-031-00595-4
Pages
1 –17
DOI
10.1007/978-3-031-01723-0_1
Publisher site
See Chapter on Publisher Site

Abstract

[For many years, most computer architects have pursued one primary goal: performance. Architects have translated the ever-increasing abundance of ever-faster transistors provided by Moore’s law into remarkable increases in performance. Recently, however, the bounty provided by Moore’s law has been accompanied by several challenges that have arisen as devices have become smaller, including a decrease in dependability due to physical faults. In this book, we focus on the dependability challenge and the fault tolerance solutions that architects are developing to overcome it.]

Published: Jan 1, 2009

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