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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-ChipArchitectural Reliability Estimation

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip:... [In this chapter, three high-level reliability estimation techniques are illustrated which fast characterize the effects of errors on processor architecture.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-ChipArchitectural Reliability Estimation

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/lp/springer-journals/high-level-estimation-and-exploration-of-reliability-for-multi-0JH0edKSH6
Publisher
Springer Singapore
Copyright
© Springer Science+Business Media Singapore 2018
ISBN
978-981-10-1072-9
Pages
81 –117
DOI
10.1007/978-981-10-1073-6_5
Publisher site
See Chapter on Publisher Site

Abstract

[In this chapter, three high-level reliability estimation techniques are illustrated which fast characterize the effects of errors on processor architecture.]

Published: Jun 24, 2017

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