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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-ChipArchitectural Reliability Exploration

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip:... [In this chapter, three architecture-level fault tolerant techniques are presented. In Sect. 6.1 opportunistic redundancy is proposed to protect the algorithmic units of embedded processor with a low performance penalty. In Sect. 6.2 asymmetric redundancy is proposed to protect the memory elements with the feature of unequal error protection based on information criticality. In Sect. 6.3 error confinement technique is proposed to correct errors in memory with statistical data, which reaches similar protection level with faster performance and less power consumption than traditional techniques.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-ChipArchitectural Reliability Exploration

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Publisher
Springer Singapore
Copyright
© Springer Science+Business Media Singapore 2018
ISBN
978-981-10-1072-9
Pages
119 –153
DOI
10.1007/978-981-10-1073-6_6
Publisher site
See Chapter on Publisher Site

Abstract

[In this chapter, three architecture-level fault tolerant techniques are presented. In Sect. 6.1 opportunistic redundancy is proposed to protect the algorithmic units of embedded processor with a low performance penalty. In Sect. 6.2 asymmetric redundancy is proposed to protect the memory elements with the feature of unequal error protection based on information criticality. In Sect. 6.3 error confinement technique is proposed to correct errors in memory with statistical data, which reaches similar protection level with faster performance and less power consumption than traditional techniques.]

Published: Jun 24, 2017

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