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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-ChipIntroduction

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip:... [The last few decades have witnessed continuous scaling of CMOS technology, guided by Moore’s Law [136] (G.E. Moore, 38(8), 114 ff, 1965. IEEE Solid-State Circuits Newsl., 3(20), 33–35, 2006), to support devices with higher speed, less area, and less power.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-ChipIntroduction

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/lp/springer-journals/high-level-estimation-and-exploration-of-reliability-for-multi-guSpdsFS50
Publisher
Springer Singapore
Copyright
© Springer Science+Business Media Singapore 2018
ISBN
978-981-10-1072-9
Pages
1 –4
DOI
10.1007/978-981-10-1073-6_1
Publisher site
See Chapter on Publisher Site

Abstract

[The last few decades have witnessed continuous scaling of CMOS technology, guided by Moore’s Law [136] (G.E. Moore, 38(8), 114 ff, 1965. IEEE Solid-State Circuits Newsl., 3(20), 33–35, 2006), to support devices with higher speed, less area, and less power.]

Published: Jun 24, 2017

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