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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-ChipConclusion and Outlook

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip:... [Continuous technology scaling in semiconductor industry forces reliability as a serious design concern in the era of nanoscale computing. Traditional low-level reliability estimation and fault tolerant techniques neither address the huge design complexity of modern system-on-chip nor consider architectural and system-level error masking properties.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

High-level Estimation and Exploration of Reliability for Multi-Processor System-on-ChipConclusion and Outlook

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Publisher
Springer Singapore
Copyright
© Springer Science+Business Media Singapore 2018
ISBN
978-981-10-1072-9
Pages
177 –179
DOI
10.1007/978-981-10-1073-6_8
Publisher site
See Chapter on Publisher Site

Abstract

[Continuous technology scaling in semiconductor industry forces reliability as a serious design concern in the era of nanoscale computing. Traditional low-level reliability estimation and fault tolerant techniques neither address the huge design complexity of modern system-on-chip nor consider architectural and system-level error masking properties.]

Published: Jun 24, 2017

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