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Low-power test pattern generator using modified LFSR

Low-power test pattern generator using modified LFSR Low-power designs are getting increased significance in numerous applications like high-performance computing and wireless communication due to the rise in power dissipation. Power dissipation of VLSI (very large scale integration) circuits in test mode is much higher than in the normal operation mode due to the high frequency of applied test patterns. Product lifetime, yield, reduced performance, and circuit damage will result from this additional power consumption in testing. Therefore, the main objective of today’s test applications is to minimize power dissipation by increasing the correlation of applied successive test vectors. Low-power test pattern generator (TPG) using LFSR (linear feedback shift register) and binary to the excess-4 converter and binary ripple counter is proposed. The test vectors generated by the TPG have a high correlation between successive test vectors, which leads to minimum switching. During the testing of benchmark circuits, the proposed method shows a significant reduction in dynamic power consumption concerning its peer works. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Aerospace Systems Springer Journals

Low-power test pattern generator using modified LFSR

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Publisher
Springer Journals
Copyright
Copyright © Shanghai Jiao Tong University 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
ISSN
2523-3947
eISSN
2523-3955
DOI
10.1007/s42401-022-00191-5
Publisher site
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Abstract

Low-power designs are getting increased significance in numerous applications like high-performance computing and wireless communication due to the rise in power dissipation. Power dissipation of VLSI (very large scale integration) circuits in test mode is much higher than in the normal operation mode due to the high frequency of applied test patterns. Product lifetime, yield, reduced performance, and circuit damage will result from this additional power consumption in testing. Therefore, the main objective of today’s test applications is to minimize power dissipation by increasing the correlation of applied successive test vectors. Low-power test pattern generator (TPG) using LFSR (linear feedback shift register) and binary to the excess-4 converter and binary ripple counter is proposed. The test vectors generated by the TPG have a high correlation between successive test vectors, which leads to minimum switching. During the testing of benchmark circuits, the proposed method shows a significant reduction in dynamic power consumption concerning its peer works.

Journal

Aerospace Systems – Springer Journals

Published: Jan 9, 2023

Keywords: Benchmark circuits; Test pattern generator; LFSR; Test power

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