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Memristor-Based Nanoelectronic Computing Circuits and ArchitecturesMemristive Computing for NP-Hard AI Problems

Memristor-Based Nanoelectronic Computing Circuits and Architectures: Memristive Computing for... [Reported properties of network configurations of memristors, as presented in Chap. 7, showed that composite memristive systems significantly improve the efficiency of logic operations via massive analog parallelism. The sparse nature of such network-based computations, though, resembles certain operational features and computing capabilities of Cellular Automata (CA), a powerful parallel computational model which leads to scalable hardware (HW) architectures with very high device densities. When CA-based models are implemented in HW, the circuit design reduces to the design of a single cell and the overall layout results regular with exclusively local inter-connections. Moreover, the models are executed fast by exploiting the parallelism of the CA structure. This chapter focuses on a circuit-level CA-inspired approach for in-memory computing schemes using memristors and composite memristive components. A generalized CA cell circuit design methodology is described, which facilitates the implementation of CA-based computing algorithms, exploiting the threshold-type resistance switching behavior of memristors and of multi-state memristive components. Several CA cell example structures are designed and employed in array-like circuit geometries, where computations regarding classic NP-hard problems of various areas of artificial intelligence (AI) take place. The main contribution of this methodology consists in the combination of unconventional computing with CA and the unique circuit properties of memristors, aiming to set off parallel computing capabilities and improve CA-based hardware accelerators for NP-hard AI problems.] http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png

Memristor-Based Nanoelectronic Computing Circuits and ArchitecturesMemristive Computing for NP-Hard AI Problems

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Publisher
Springer International Publishing
Copyright
© Springer International Publishing Switzerland 2016
ISBN
978-3-319-22646-0
Pages
199 –241
DOI
10.1007/978-3-319-22647-7_8
Publisher site
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Abstract

[Reported properties of network configurations of memristors, as presented in Chap. 7, showed that composite memristive systems significantly improve the efficiency of logic operations via massive analog parallelism. The sparse nature of such network-based computations, though, resembles certain operational features and computing capabilities of Cellular Automata (CA), a powerful parallel computational model which leads to scalable hardware (HW) architectures with very high device densities. When CA-based models are implemented in HW, the circuit design reduces to the design of a single cell and the overall layout results regular with exclusively local inter-connections. Moreover, the models are executed fast by exploiting the parallelism of the CA structure. This chapter focuses on a circuit-level CA-inspired approach for in-memory computing schemes using memristors and composite memristive components. A generalized CA cell circuit design methodology is described, which facilitates the implementation of CA-based computing algorithms, exploiting the threshold-type resistance switching behavior of memristors and of multi-state memristive components. Several CA cell example structures are designed and employed in array-like circuit geometries, where computations regarding classic NP-hard problems of various areas of artificial intelligence (AI) take place. The main contribution of this methodology consists in the combination of unconventional computing with CA and the unique circuit properties of memristors, aiming to set off parallel computing capabilities and improve CA-based hardware accelerators for NP-hard AI problems.]

Published: Aug 27, 2015

Keywords: Memristor State; Analog Memristor; Knapsack; Reset Stage; Memristor Model

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