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Ultrathin Wafer Pre-Assembly and Assembly Process Technologies: A Review

Ultrathin Wafer Pre-Assembly and Assembly Process Technologies: A Review Ultrathin silicon wafer technology is reviewed in terms of the semiconductor applications, critical challenges, and wafer pre-assembly and assembly process technologies and their underlying mechanisms. Mechanical backgrinding has been the standard process for wafer thinning in the semiconductor industry owing to its low cost and productivity. As the thickness requirement of wafers is reduced to below 100 μm, many challenges are being faced due to wafer/die bow, mechanical strength, wafer handling, total thickness variation (TTV), dicing, and packaging assembly. Various ultrathin wafer processing and assembly technologies have been developed to address these challenges. These include wafer carrier systems to handle ultrathin wafers; backgrinding subsurface damage and surface roughness reduction, and post-grinding treatment to increase wafer/die strength; improved wafer carrier flatness and backgrinding auto-TTV control to improve TTV; wafer dicing technologies to reduce die sidewall damage to increase die strength; and assembly methods for die pick-up, die transfer, die attachment, and wire bonding. Where applicable, current process issues and limitations, and future work needed are highlighted. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Critical Reviews in Solid State and Materials Sciences Taylor & Francis

Ultrathin Wafer Pre-Assembly and Assembly Process Technologies: A Review

40 pages

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References (224)

Publisher
Taylor & Francis
Copyright
Copyright © Taylor & Francis Group, LLC
ISSN
1547-6561
eISSN
1040-8436
DOI
10.1080/10408436.2014.992585
Publisher site
See Article on Publisher Site

Abstract

Ultrathin silicon wafer technology is reviewed in terms of the semiconductor applications, critical challenges, and wafer pre-assembly and assembly process technologies and their underlying mechanisms. Mechanical backgrinding has been the standard process for wafer thinning in the semiconductor industry owing to its low cost and productivity. As the thickness requirement of wafers is reduced to below 100 μm, many challenges are being faced due to wafer/die bow, mechanical strength, wafer handling, total thickness variation (TTV), dicing, and packaging assembly. Various ultrathin wafer processing and assembly technologies have been developed to address these challenges. These include wafer carrier systems to handle ultrathin wafers; backgrinding subsurface damage and surface roughness reduction, and post-grinding treatment to increase wafer/die strength; improved wafer carrier flatness and backgrinding auto-TTV control to improve TTV; wafer dicing technologies to reduce die sidewall damage to increase die strength; and assembly methods for die pick-up, die transfer, die attachment, and wire bonding. Where applicable, current process issues and limitations, and future work needed are highlighted.

Journal

Critical Reviews in Solid State and Materials SciencesTaylor & Francis

Published: Sep 3, 2015

Keywords: ultrathin wafer; ultrathin die; wafer carrier; wafer backgrinding; post-grinding treatment; wafer dicing; packaging assembly

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